1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a contact structure for a vertical channel semiconductor device and the resulting device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, omega gate devices, gate-all-around (GAO) devices, such as nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
The channel structure of these various FET devices may be oriented substantially horizontal or substantially vertical relative to a reference planar upper surface of a semiconductor substrate. In FETs with a horizontally oriented channel structure, the current passing through the channel region of the device (when the device is “ON”) travels in a direction that is substantially parallel to the reference planar upper surface of the semiconductor substrate. In contrast, in FETs with a vertically oriented channel structure, the current passing through the channel region of the device (when the device is “ON”) travels in a direction that is substantially perpendicular to the reference planar upper surface of the semiconductor substrate.
FIG. 1 is a simplistic depiction of a prior art vertical channel device (a nanowire device) 10 with a gate-all-around gate structure. The device 10 is formed above a semiconductor substrate 12. The device 10 includes a vertical nanowire semiconductor structure 14, a gate structure 18, a plurality of layers of insulating material 16, 20, 20A and an upper conductive structure 22. The vertical nanowire semiconductor structure 14 is comprised of a lower source/drain region 15L, an upper source/drain region 15U and a channel region 17. The device 10 also includes an illustrative contact structure 26 for establishing electrical connection to the upper source/drain region 15U (via the conductive structure 22), an illustrative contact structure 28 for establishing electrical connection to the gate structure 18, and an illustrative contact structure 30 for establishing electrical connection to the lower source/drain region 15L (via the substrate 12). The contact structures 26, 28 and 30 may not all be positioned within the same plane as depicted in FIG. 1. Establishing electrical contact to the lower source/drain region 15L via the substrate 12 is problematic due to, among other things, the relatively long distance 32 that is typically found in some devices between the contact area and the lower source/drain region 15L. Moreover, the substrate 12 itself defines a relatively high resistance path for the flow of current from the contact 30 to the lower source/drain region 15L, thereby reducing device performance.
The present disclosure is directed to various methods of forming a contact structure for a vertical channel semiconductor device and the resulting device that may avoid, or at least reduce, the effects of one or more of the problems identified above.